A matrix-type display apparatus includes a plurality of data lines to which picture signals are inputted, and a plurality of scanning lines provided so as to intersect the data lines so that the picture signals thus inputted to the data lines are scanned during each scanning period. At intersections of the data and scanning lines, there are provided pixels which carry out display in accordance with the picture signals supplied by the data lines. The pixels in whole are provided in a matrix form over the screen. Such a matrix-type display apparatus requires scanning signals issued by a scanning circuit so as to sample the inputted picture signals during one scanning period.
A conventional scanning circuit is provided with, for example, a shift register 51 and AND circuits AG.sub.51 through AG.sub.55, as shown in FIG. 8.
As shown in FIG. 9, clocked inverters 51a and 51b and an inverter 51c constitute a one-stage circuit, and a plurality of such circuits are cascaded, thereby constituting the shift register 51. The shift register 51 shifts a start pulse supplied by a pulse line PL, sequentially from one stage of the circuits to next, in response to a clock signal supplied by a clock line CKL. The start pulse thus supplied to each circuit is outputted through output lines SOL.sub.51 through SOL.sub.56 provided to the respective stages.
To be more concrete, as shown in FIG. 10, the start pulse STP is transferred to the stages one by one in synchronization with the clock signal CK, and is outputted through the output lines SOL.sub.51 through SOL.sub.56 as shift pulses SP.sub.51 through SP.sub.56, respectively. The shift pulses S.sub.51, S.sub.52, S.sub.53, S.sub.54, S.sub.55, and S.sub.56 are outputted in this order at the following timings: The odd-numbered shift pulses SP.sub.51, SP.sub.53, and SP.sub.55 are outputted at timings in synchronization with rises of the clock signal CK, while the even-numbered shift pulses SP.sub.52, SP.sub.54, and SP.sub.56 are outputted at timings in synchronization with falls of the clock signal CK.
Pairs of the output lines SOL.sub.51 through SOL.sub.56, one pair being composed of neighboring two output lines, are connected to the AND circuits AG.sub.51 through AG.sub.55, respectively. The two shift pulses are inputted to each of the AND circuits AG.sub.51 through AG.sub.55 through the respective two output lines, and each AND circuit AG conducts an AND operation on the two shift pulses. As a result, scanning signals SS.sub.51 through SS.sub.55 which have respective timings and the same pulse duration as that of the clock signal CK are outputted by the AND circuits AG.sub.51 through AG.sub.55 to output lines OL.sub.51 through OL.sub.55, respectively.
Another conventional scanning circuit is a decoder-type scanning circuit provided with, for example, as shown in FIG. 11(a), address lines AL.sub.61 through AL.sub.63, address lines IAL.sub.61 through IAL.sub.63, and AND circuits AG.sub.61 through AG.sub.68 which constitute a decoder.
As shown in FIG. 11(b), inputted to the address line AL.sub.61 is a bit signal BS.sub.61 with a cycle of T and a duty factor of 50 percent. Inputted to the address lines AL.sub.62 and AL.sub.63 are a bit signal BS.sub.62 with a cycle of 2T and a bit signal BS.sub.63 with a cycle of 4T, respectively. On the other hand, inputted to the address lines IAL.sub.61 through IAL.sub.63 are bit signals IBS.sub.61 through IBS.sub.63, respectively, which are obtained by inverting the bit signals BS.sub.61 through BS.sub.63.
The AND circuit AG.sub.61 is connected to the address lines IAL.sub.61 through IAL.sub.63. The AND circuit AG.sub.62 is connected to the address lines AL.sub.61, IAL.sub.62, and IAL.sub.63. The AND circuit AG.sub.63 is connected to the address lines AL.sub.62, IAL.sub.61, and IAL.sub.63. The AND circuit AG.sub.64 is connected to the address lines AL.sub.61, AL.sub.62, and IAL.sub.63. The AND circuit AG.sub.65 is connected to the address lines AL.sub.63, IAL.sub.61, and IAL.sub.62. The AND circuit AG.sub.66 is connected to the address lines AL.sub.61, AL.sub.63, and IAL.sub.62. The AND circuit AG.sub.67 is connected to the address lines AL.sub.62, AL.sub.63, and IAL.sub.61. The AND circuit AG.sub.68 is connected to the address lines AL.sub.61 through AL.sub.63.
The AND circuits AG.sub.61 through AG.sub.68 are thus supplied with three bit signals each, one combination of three bit signals constituting the address signal never being the same as another, and conduct AND operations on the address signal. As a result, a pulse with a pulse duration of T/2 is supplied, sequentially with a delay of T/2 each time, from the AND circuits AG.sub.61 through AG.sub.68 to output lines OL.sub.61 through OL.sub.68, respectively. Thus, scanning signals SS.sub.61 through SS.sub.68 shown in FIG. 11(b) are outputted. Combinations of binary values of the respective bits constituting the address signal to which the output timings of the pulse correspond are shown in Table 1 below.
TABLE 1 ______________________________________ ADDRESS SIGNAL SCANNING BS.sub.61 BS.sub.62 BS.sub.63 SIGNAL ______________________________________ 0 0 0 SS.sub.61 0 0 1 SS.sub.62 0 1 0 SS.sub.63 0 1 1 SS.sub.64 1 0 0 SS.sub.65 1 0 1 SS.sub.66 1 1 0 SS.sub.67 1 1 1 SS.sub.68 ______________________________________
The following description will discuss comparison between two data line driving circuits for use in a matrix-type display apparatus, to which the above-described scanning circuits are respectively applied.
The clock signal inputted to the shift register and the least significant bit (bit signal BS.sub.61) of the address signal inputted to the decoder are determined depending on a dot frequency f.sub.d respectively and have a frequency equivalent to half of the dot frequency f.sub.d. Note that the dot frequency f.sub.d is a reciprocal of a period of time required for reading a quantity of data which is equivalent to one pixel of the matrix-type display apparatus.
The following description will discuss comparison between the two data line driving circuits about their consumption of power.
Given a frequency f, a load capacity C, and a power source voltage V, power consumption P is defined as P=fCV.sup.2. Here, to simplify the calculation, the load capacity C is restricted to gate input capacities of transistors composing the respective scanning circuits.
In the data line driving circuit using the shift register, as shown in FIG. 12, the clocked inverters 51a, disposed on a line through which the start pulse STP is transferred, are equipped with an N-type transistor T.sub.n51 and a P-type transistor T.sub.p51 each, to which a clock signal CK and an inverted clock signal /CK are respectively inputted. Each stage of the circuits constituting the shift register 51 has two clocked inverters, namely, clocked inverters 51a and 51b.
Therefore, given that the transistors T.sub.n51 and T.sub.p51 have an input capacity C.sub.g each and that the shift register 51 has L outputs, the single clock line CKL has a load capacity C.sub.sf of 2LC.sub.g. In addition, the clock line CKL is actually composed of two signal lines for outputting the clock signal CK and the inverted clock signal /CK, respectively.
Accordingly, the power consumption P.sub.sf of the shift register 51 is obtained by the following equation: ##EQU1## wherein the frequency of the clock signal is f.sub.d /2, as described above.
The data line driving circuit of the decoder type has a decoder actually composed of CMOS circuits. Therefore, instead of the AND circuits AG, either NAND circuits 52 (see FIG. 13) or NOR circuits (not shown), which execute logical operation similar to that by the AND circuits AG. Each NAND circuit 52 has pairs of an N-type transistor T.sub.n52 and a P-type transistor T.sub.p52, and the number of the pairs in one NAND circuit 52 corresponds to the number of address lines AL and IAL connected to one NAND circuit 52, that is, the number of inputs thereto. Note that the NAND circuit 52 shown in FIG. 13 is arranged so that two inputs are supplied to the NAND circuit 52.
Therefore, in the case where the NAND circuits 52 are connected to address lines AL at a rate of L/2 NAND circuits 52 per one address line AL, the total number of the transistors T.sub.n52 and T.sub.p52 connected to one address line AL is L. Accordingly, when the respective input capacities of the transistors T.sub.n52 and T.sub.p52 are defined as C.sub.g each, the load capacity C.sub.a per one address line AL is given as LC.sub.g (=C.sub.sf /2).
The frequency of the least significant bit of the address signal is f.sub.d /2, as described above. When the number of the provided address lines AL is m, the bits of the address signal are set so as to have frequencies f.sub.d /2, f.sub.d /2.sup.2, f.sub.d /2.sup.3, f.sub.d /2.sup.4, . . . , f.sub.d /2.sup.m-2, f.sub.d /2.sup.m-1, f.sub.d /2.sup.m, from the least significant bit to the most significant bit. Furthermore, when the data line driving circuit has m address lines AL, it also has the same number m of address lines IAL to which the inverted clock signals are inputted. Therefore, the total number of the address lines AL and IAL is 2m.
Therefore, the power consumption P.sub.a of the decoder is obtained by the following equation: ##EQU2## Thus, the power consumption of the data line driving circuit of the decoder type is substantially the same as that of the data line driving circuit of the shift register type.
Comparison is made between the two data line driving circuits about scanning speed, in the following description.
In the case with the data line driving circuit of the shift register type, a signal is subsequently transferred from one stage to another in the shift register 51, wherein an input signal to one stage is supplied by its previous stage. Therefore, the input signal has been affected by delay or rounding of the waveform which has been caused in the previous stages. In addition, an operational speed is affected by respective driving capacities of the individual transistors, the output signal from the previous stages, and input capacities of the following stages. Furthermore, a period while the P-type transistor and the N-type transistor in each inverter are simultaneously in the ON state is prolonged due to the rounding of the signal waveform. Such phenomena cause a current to increase, thereby increase the power consumption.
In the data line driving circuit of the decoder type, the address signal is directly inputted from the respective address lines AL to the corresponding logical circuits in the decoder. Therefore, the address signal is not affected by other circuits. Furthermore, whereas each stage of the shift register 51 is connected to two circuit systems, namely, the following stage and an output buffer (not shown), each logical circuit of the decoder is connected only to a buffer so as to supply an output thereto. Accordingly, one logical circuit of the decoder has an input load of a following stage, which is only half of that of one stage of the shift register, thereby having a higher operating speed.
Since the input load (capacity) of the following stage for the decoder is half of that of the shift register 51 as mentioned above, the decoder has less rounding of the signal waveform compared with the shift register. Accordingly, the current of the decoder is smaller than that of the shift register 51. Therefore, the decoder is superior in the power consumption as well.
In addition, the data line driving circuit of the decoder type is superior in the yield, as described below.
The data line driving circuit of the shift register type presents a problem pointed out in the Japanese Laid-open Patent Publication 7-191636/1995. Each stage of a shift register has 10 transistors, and each AND circuit thereof has 6 transistors, for example. Therefore, one data line driving circuit is composed of a large number of transistors. This leads to a low non-defective ratio of the data line driving circuit of the shift register type. In addition, in the case where the data line driving circuit and a display panel are integrally provided by using polycrystalline silicon, this leads to a problem that a ratio of non-defective operation of transistors further decreases due to dispersion in characteristics, electrostatic breakdown, etc.
In contrast, since the data line driving circuit of the decoder type has less transistors per one output, as described in the foregoing publication, it has a non-defective ratio higher than that of the data line driving circuit of the shift register type.
As has been described, the data line driving circuit of the decoder type is superior to the data line driving circuit of the shift register type in practical application.
Regarding the scanning circuit of the decoder type described above, an output is selected according to the combinations of the binary values of the bits constituting the address signal, as shown in FIG. 11(b). When the address signal carries, sometimes plural bits among those constituting the address signal are simultaneously switched, for example, from "011" to "100", as shown in Table 1. Such a switching tends to cause phase shift due to delays of the address signal or the like, thereby resulting in glitches.
In the case where the scanning circuit of the decoder type is applied to a data line driving circuit for use in a matrix-type display apparatus, frequencies of the address signal to be inputted to the decoder are determined depending on a dot frequency f.sub.d in accordance with the standard of the image display apparatus. For example, concerning a VGA (video graphics array)-standard image display apparatus, a frequency f.sub.a of a least significant bit of the address signal to be supplied to the decoder is obtained by the following equation, in consideration of a blanking period: ##EQU3## wherein H represents the number of dots in a horizontal direction, and V represents the number of dots in a vertical direction.
Models of image display apparatuses have recently been diversified, while there has been an increasing demand for higher display quality of the image display apparatuses. To cope with such a demand, application of higher frequencies to driving circuits for use in data line driving circuits has been attempted. For example, in the case with a matrix-type display apparatus of an XGA (extended graphics array) standard, with the least significant bit of the address signal to be supplied to a decoder provided in a driving circuit is required to have a frequency of around 40 MHz. Since the power consumption is given as P=fCV.sup.2, as described above, it increases in proportion to the frequency. Thus, the frequency greatly affects the power consumption.
On the other hand, there has also been an increasing demand for a matrix-type display apparatus consuming less power, and technical innovation has been promoted so as to meet the demand.
The address signal inputted to the decoder changes in the highest frequencies in those used in the scanning circuit of the image display apparatus. Furthermore, as described above, since the address lines are connected to the logical circuits at a rate of L/2 logical circuits per one address line, the address lines have a great input load capacity each. Power consumption due to the input load capacity accounts for a considerable part of the total power consumption of the data line driving circuit. Therefore, reduction in the power consumption by input members for inputting to the decoder is an important task so as to achieve reduction in the power consumption of the data line driving circuit.
Moreover, the following problem has been presented in the case where a display panel and a driving circuit are integrally formed by using polycrystalline silicon thin film transistors: for example, as mentioned in the Japanese Examined Patent Publication No. 5-22917/1993, a mobility of carriers in the silicon thin film is a fraction of carriers in silicon monocrystals. Furthermore, since refinement of the apparatus and improvement of process for such refined apparatus has been delaying, a limit of an operational speed of the polycrystalline silicon film transistor is lower than one several tenth of that of a conventional integrated circuit.
A conventional image display apparatus provided with a driver which is realized by an integrated circuit for an exclusive use as a driver does not have such a problem as described above, thereby being driven by a single driver system. In contrast, the scanning circuit exhibits a low operational speed, in the case where the foregoing scanning circuit is adapted to a data line driving circuit (driver) which is built in an active matrix substrate in a matrix-type image display apparatus with a high resolution. Therefore, the data line driving circuit is required to have a plurality of driver systems, so as to solve the problem of the low operational speed.
This stems from that the transistors are affected by variations of characteristics of the circuit, in addition to that the individual transistors each have a low driving capacity. Therefore, a scanning circuit which can be operated at lower frequencies has been sought for.